4305 search results - page 4 / 861 » The Test of Time |
130
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DAC
2002
ACM
16 years 6 months ago
2002
ACM
We propose a false-path-aware statistical timing analysis framework. In our framework, cell as well as interconnect delays are assumed to be correlated random variables. Our tool ...
155
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DFT
2004
IEEE
15 years 9 months ago
2004
IEEE
This paper proposes a test architecture aimed at reducing test time of distributed small embedded SRAMs (eSRAMs). This architecture improves the one proposed in [4, 5]. The improv...
140
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DATE
2002
IEEE
15 years 10 months ago
2002
IEEE
We present a new test resource partitioning (TRP) technique for reduced pin-count testing of system-on-a-chip (SOC). The proposed technique is based on test data compression and o...
178
Voted
DFT
2002
IEEE
15 years 10 months ago
2002
IEEE
Conversion of the flip-flops of the circuit into scan cells helps ease the test challenge; yet test application time is increased as serial shift operations are employed. Furthe...