4305 search results - page 50 / 861 » The Test of Time |
161
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DAGSTUHL
2007
15 years 7 months ago
2007
In this paper we give the first deterministic polynomial time algorithm for testing whether a diagonal depth-3 circuit C(x1, . . . , xn) (i.e. C is a sum of powers of linear funct...
139
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ISQED
2002
IEEE
15 years 10 months ago
2002
IEEE
This paper presents a hybrid BIST architecture and methods for optimizing it to test systems-on-chip in a cost effective way. The proposed self-test architecture can be implemente...
128
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ATS
2004
IEEE
15 years 9 months ago
2004
IEEE
Conventional serial connection of internal scan chains brings the power and time penalty. A novel parallel core wrapper design (pCWD) approach is presented in this paper for reduc...
142
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GLOBECOM
2008
IEEE
16 years 7 days ago
2008
IEEE
—Research in cognitive radios has renewed interest in tools, such as spectrum estimation and modulation identification, to characterize the radio frequency (RF) environment. The...
167
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VLSID
2009
IEEE
16 years 6 months ago
2009
IEEE
Functional validation is a major bottleneck in the current SOC design methodology. While specification-based validation techniques have proposed several promising ideas, the time ...