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DATE
2009
IEEE
138views Hardware» more  DATE 2009»
16 years 17 days ago
Scalable Adaptive Scan (SAS)
Scan compression has emerged as the most successful solution to solve the problem of rising manufacturing test cost. Compression technology is not hierarchical in nature. Hierarch...
Anshuman Chandra, Rohit Kapur, Yasunari Kanzawa
ICCAD
1995
IEEE
94views Hardware» more  ICCAD 1995»
15 years 9 months ago
Test register insertion with minimum hardware cost
Implementing a built-in self-test by a "test per clock" scheme offers advantages concerning fault coverage, detection of delay faults, and test application time. Such a ...
Albrecht P. Stroele, Hans-Joachim Wunderlich
ICST
2008
IEEE
16 years 6 days ago
On the Predictability of Random Tests for Object-Oriented Software
Intuition suggests that random testing of object-oriented programs should exhibit a high difference in the number of defects detected by two different runs over the same amount of...
Ilinca Ciupa, Alexander Pretschner, Andreas Leitne...
ICCAD
2003
IEEE
105views Hardware» more  ICCAD 2003»
16 years 2 months ago
TAM Optimization for Mixed-Signal SOCs using Analog Test Wrappers
We present a new approach for TAM optimization and test scheduling in the modular testing of mixed-signal SOCs. A test planning approach for digital SOCs is extended to handle ana...
Anuja Sehgal, Sule Ozev, Krishnendu Chakrabarty
ICCAD
2002
IEEE
116views Hardware» more  ICCAD 2002»
16 years 2 months ago
Conflict driven techniques for improving deterministic test pattern generation
This work presents several new techniques for enhancing the performance of deterministic test pattern generation for VLSI circuits. The techniques introduced are called dynamic de...
Chen Wang, Sudhakar M. Reddy, Irith Pomeranz, Xiji...