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ISVLSI
2008
IEEE
136views VLSI» more  ISVLSI 2008»
16 years 6 days ago
A Real Case of Significant Scan Test Cost Reduction
With the advent of nanometer technologies, the design size of integrated circuits is getting larger and the operation speed is getting faster. As a consequence, test cost is becom...
Selina Sha, Bruce Swanson
135
Voted
ATS
2009
IEEE
99views Hardware» more  ATS 2009»
16 years 19 days ago
Test Generation for Designs with On-Chip Clock Generators
High performance designs often use the on-chip device PLLs for accurate test clock generation during testing. The on-chip clock generator is designed in a programmable way to faci...
Xijiang Lin, Mark Kassab
168
Voted
ISCAS
2011
IEEE
210views Hardware» more  ISCAS 2011»
14 years 9 months ago
A mostly-digital analog scan-out chain for low bandwidth voltage measurement for analog IP test
—A method of precise measurement of on-chip analog voltages in a mostly-digital manner, with minimal overhead, is presented. A pair of clock signals is routed to the node of an a...
Rajath Vasudevamurthy, Pratap Kumar Das, Bharadwaj...
DATE
2000
IEEE
121views Hardware» more  DATE 2000»
15 years 10 months ago
Functional Test Generation for Full Scan Circuits
We study the effectiveness of functional tests for full scan circuits. Functional tests are important for design validation, and they potentially have a high defect coverage indep...
Irith Pomeranz, Sudhakar M. Reddy
TSMC
2008
94views more  TSMC 2008»
15 years 5 months ago
Test Sequencing in Complex Manufacturing Systems
Testing complex manufacturing systems, such as an ASML [1] lithographic machine, takes up to 45% of the total development time of a system. The problem of which tests must be execu...
R. Boumen, I. S. M. de Jong, J. W. H. Vermunt, J. ...