Sciweavers

4305 search results - page 68 / 861
» The Test of Time
Sort
View
DATE
2005
IEEE
139views Hardware» more  DATE 2005»
15 years 11 months ago
Statistical Timing Analysis with Extended Pseudo-Canonical Timing Model
— State of the art statistical timing analysis (STA) tools often yield less accurate results when timing variables become correlated due to global source of variations and path r...
Lizheng Zhang, Weijen Chen, Yuhen Hu, Charlie Chun...
ICTAI
2002
IEEE
15 years 10 months ago
A Genetic Testing Framework for Digital Integrated Circuits
In order to reduce the time-to-market and simplify gatelevel test generation for digital integrated circuits, GAbased functional test generation techniques are proposed for behavi...
Xiaoming Yu, Alessandro Fin, Franco Fummi, Elizabe...
ISSTA
1993
ACM
15 years 10 months ago
Faults on Its Sleeve: Amplifying Software Reliability Testing
Most of the effort that goes into improving the quality of software paradoxically does not lead to quantitative, measurable quality. Software developers and quality-assurance orga...
Richard G. Hamlet, Jeffrey M. Voas
VTS
2003
IEEE
119views Hardware» more  VTS 2003»
15 years 11 months ago
Test Data Compression Using Dictionaries with Fixed-Length Indices
—We present a dictionary-based test data compression approach for reducing test data volume and testing time in SOCs. The proposed method is based on the use of a small number of...
Lei Li, Krishnendu Chakrabarty
VLSID
2002
IEEE
131views VLSI» more  VLSID 2002»
16 years 6 months ago
Divide-and-Conquer IDDQ Testing for Core-Based System Chips
IDDQ testing has been used as a test technique to supplement voltage testing of CMOS chips. The idea behind IDDQ testing is to declare a chip as faulty if the steady-state current...
C. P. Ravikumar, Rahul Kumar