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» The Test of Time
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VTS
2002
IEEE
138views Hardware» more  VTS 2002»
15 years 11 months ago
Test Power Reduction through Minimization of Scan Chain Transitions
Parallel test application helps reduce the otherwise considerable test times in SOCs; yet its applicability is limited by average and peak power considerations. The typical test v...
Ozgur Sinanoglu, Ismet Bayraktaroglu, Alex Orailog...
ICCAD
2000
IEEE
100views Hardware» more  ICCAD 2000»
15 years 10 months ago
Partial Simulation-Driven ATPG for Detection and Diagnosis of Faults in Analog Circuits
In this paper, we propose a novel fault-oriented test generation methodology for detection and isolation of faults in analog circuits. Given the description of the circuit-underte...
Sudip Chakrabarti, Abhijit Chatterjee
APSEC
2009
IEEE
15 years 3 months ago
A Formal Framework to Integrate Timed Security Rules within a TEFSM-Based System Specification
Abstract--Formal methods are very useful in software industry and are becoming of paramount importance in practical engineering techniques. They involve the design and the modeling...
Wissam Mallouli, Amel Mammar, Ana R. Cavalli
UAI
2008
15 years 7 months ago
CT-NOR: Representing and Reasoning About Events in Continuous Time
We present a generative model for representing and reasoning about the relationships among events in continuous time. We apply the model to the domain of networked and distributed...
Aleksandr Simma, Moisés Goldszmidt, John Ma...
SIGDOC
2005
ACM
15 years 11 months ago
Usability over time
Testing of usability could perhaps be more accurately described as testing of learnability. We know more about the problems of novice users than we know of the problems of experie...
Valerie Mendoza, David G. Novick