Test application time is an important factor in the overall cost of VLSI chip testing. We present a new ATPG approach for generating compact test sequences for sequential circuits...
Yanti Santoso, Matthew C. Merten, Elizabeth M. Rud...
Abstract-- In this paper a novel pulse sequence testing methodology is presented [22] as an alternative to Time Domain Reflectometry (TDR) for transmission line health condition mo...
Object-orientation has rapidly become accepted as the preferred paradigm for large scale system design. There is considerable literature describing approaches to object-oriented d...
Core-based system-on-chips (SoCs) fabricated on threedimensional (3D) technology are emerging for better integration capabilities. Effective test architecture design and optimizat...
This paper presents a new approach to speed up the operation of time delay neural networks for fast code detection. The entire data are collected together in a long vector and then...