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» The Test of Time
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DATE
1999
IEEE
120views Hardware» more  DATE 1999»
15 years 10 months ago
FreezeFrame: Compact Test Generation Using a Frozen Clock Strategy
Test application time is an important factor in the overall cost of VLSI chip testing. We present a new ATPG approach for generating compact test sequences for sequential circuits...
Yanti Santoso, Matthew C. Merten, Elizabeth M. Rud...
JCP
2006
92views more  JCP 2006»
15 years 6 months ago
A Novel Pulse Echo Correlation Tool for Transmission Path Testing and Fault Diagnosis
Abstract-- In this paper a novel pulse sequence testing methodology is presented [22] as an alternative to Time Domain Reflectometry (TDR) for transmission line health condition mo...
David M. Horan, Richard A. Guinee
TOOLS
1998
IEEE
15 years 10 months ago
Support for Object-Oriented Testing
Object-orientation has rapidly become accepted as the preferred paradigm for large scale system design. There is considerable literature describing approaches to object-oriented d...
Michael Kölling, John Rosenberg
DATE
2009
IEEE
98views Hardware» more  DATE 2009»
16 years 23 days ago
Test architecture design and optimization for three-dimensional SoCs
Core-based system-on-chips (SoCs) fabricated on threedimensional (3D) technology are emerging for better integration capabilities. Effective test architecture design and optimizat...
Li Jiang, Lin Huang, Qiang Xu
ISNN
2007
Springer
16 years 4 days ago
Fast Code Detection Using High Speed Time Delay Neural Networks
This paper presents a new approach to speed up the operation of time delay neural networks for fast code detection. The entire data are collected together in a long vector and then...
Hazem M. El-Bakry, Nikos E. Mastorakis