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LCPC
2005
Springer
15 years 4 months ago
Compiler Supports and Optimizations for PAC VLIW DSP Processors
Abstract. Compiler is substantially regarded as the most essential component in the software toolchain to promote a successful processor design. This paper describes our preliminar...
Yung-Chia Lin, Chung-Lin Tang, Chung-Ju Wu, Ming-Y...
ERSA
2009
147views Hardware» more  ERSA 2009»
14 years 8 months ago
Fault Avoidance in Medium-Grain Reconfigurable Hardware Architectures
Medium-grain reconfigurable hardware (MGRH) architectures represent a hybrid between the versatility of a field programmable gate array (FPGA) and the computational power of a cust...
Kylan Robinson, José G. Delgado-Frias
ASC
2004
14 years 11 months ago
Efficient fuzzy compiler for SIMD architectures
Abstract. This paper presents a real-time full-programmable fuzzy compiler based on piecewise linear interpolation techniques designed to be executed in SIMD (Single Instruction Mu...
Enrique Frías-Martínez, Julio Guti&e...
RTCSA
2006
IEEE
15 years 5 months ago
Integrating Compiler and System Toolkit Flow for Embedded VLIW DSP Processors
To support high-performance and low-power for multimedia applications and for hand-held devices, embedded VLIW DSP processors are of research focus. With the tight resource constr...
Chi Wu, Kun-Yuan Hsieh, Yung-Chia Lin, Chung-Ju Wu...
DAC
1994
ACM
15 years 3 months ago
Memory Estimation for High Level Synthesis
Abstract -- This paper describes a new memory estimation technique for DSP applications written in an applicative language. Since no concept of storage is present in an applicative...
Ingrid Verbauwhede, Chris J. Scheers, Jan M. Rabae...