193 search results - page 16 / 39 » The TigerSHARC DSP Architecture |
ASAP
1997
IEEE
15 years 3 months ago
1997
IEEE
This paper presents a technique to map automatically a complete digital signal processing (DSP) application onto a parallel machine with distributed memory. Unlike other applicati...
VLSISP
2008
14 years 11 months ago
2008
ADRES (Architecture for Dynamically Reconfigurable Embedded Systems) is a templatized coarse-grained reconfigurable processor architecture. It targets at embedded applications whic...
EUROPAR
2000
Springer
15 years 2 months ago
2000
Springer
This paper investigates the potential for automatic mapping of typical embedded applications to architectures with multimedia instruction set extensions. For this purpose a (patter...
ICMCS
2006
IEEE
15 years 5 months ago
2006
IEEE
This paper provides an overview of the Parallel Architecture Core (PAC) project led by SoC Technology Center of Industrial Technology Research Institute (STC/ITRI) in Taiwan. The ...
FPGA
2000
ACM
15 years 2 months ago
2000
ACM
With increased logic density due to the shift towards Deep Submicron technologies (DSM), FPGAs have become a viable option for implementing large designs. However, most commercial...