193 search results - page 20 / 39 » The TigerSHARC DSP Architecture |
83
Voted
WCAE
2006
ACM
15 years 5 months ago
2006
ACM
At Northeastern University we are building a number of courses upon a common embedded systems platform. The goal is to reduce the learning curve associated with new architectures ...
ICMCS
2005
IEEE
15 years 4 months ago
2005
IEEE
This paper presents the optimization techniques and results of implementing the H.264/AVC baseline profile decoder in software on the Sandblaster digital signal processor. It has ...
ISCAS
2003
IEEE
15 years 4 months ago
2003
IEEE
In this paper, we use a digital signal processor (DSP) to implement a real-time H.263+ codec. We use fast algorithms to reduce the codec computational complexity. Furthermore, the...
VLSISP
1998
14 years 10 months ago
1998
This paper describes the architecture and the performance of a new programmable 16-bit Digital Signal Processor (DSP) engine. It is developed specifically for next generation wire...
112
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FPGA
2004
ACM
15 years 4 months ago
2004
ACM
In this paper, an efficient implementation of a high performance coarse-grain reconfigurable data-path on a mixed-granularity reconfigurable platform is presented. It consists of ...