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90
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IWSOC
2005
IEEE
151views Hardware» more  IWSOC 2005»
15 years 4 months ago
A Low Area and Low Power Programmable Baseband Processor Architecture
A fully programmable radio baseband processor architecture is presented. The architecture is based on a DSP processor core and a number flexible accelerators, connected via a con...
Eric Tell, Anders Nilsson, Dake Liu
DATE
2002
IEEE
118views Hardware» more  DATE 2002»
15 years 4 months ago
A Complete Data Scheduler for Multi-Context Reconfigurable Architectures
: A new technique is presented in this paper to improve the efficiency of data scheduling for multi-context reconfigurable architectures targeting multimedia and DSP applications. ...
Marcos Sanchez-Elez, Milagros Fernández, Ra...
ICMCS
2006
IEEE
136views Multimedia» more  ICMCS 2006»
15 years 5 months ago
Architecture Analysis for Low-Delay Video Coding
Low-delay video coding is a key technology for video conferencing as well as upcoming remote-monitoring and automotive video applications like rear-view cameras or night vision sy...
Ralf M. Schreier, A. Tushar Iqbal Rahman, Ganesh K...
SAMOS
2007
Springer
15 years 5 months ago
Trends in Low Power Handset Software Defined Radio
This paper presents an overview of trends in low power handset SDR implementations. With the market for SDR-enabled handsets expected to grow to 200M units by 2014, the barriers to...
John Glossner, Daniel Iancu, Mayan Moudgill, Micha...
89
Voted
DATE
2004
IEEE
122views Hardware» more  DATE 2004»
15 years 2 months ago
Phase Coupled Code Generation for DSPs Using a Genetic Algorithm
The growing use of digital signal processors (DSPs) in embedded systems necessitates the use of optimizing compilers supporting special hardware features. Due to the irregular arc...
Markus Lorenz, Peter Marwedel