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» The TigerSHARC DSP Architecture
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PLDI
2003
ACM
15 years 4 months ago
Linear analysis and optimization of stream programs
As more complex DSP algorithms are realized in practice, an increasing need for high-level stream abstractions that can be compiled without sacrificing efficiency. Toward this en...
Andrew A. Lamb, William Thies, Saman P. Amarasingh...
IEEEPACT
2000
IEEE
15 years 3 months ago
aSOC: A Scalable, Single-Chip Communications Architecture
As on-chip integration matures, single-chip system designers must not only be concerned with component-level issues such as performance and power, but also with onchip system-leve...
Jian Liang, Sriram Swaminathan, Russell Tessier
CHES
2008
Springer
134views Cryptology» more  CHES 2008»
15 years 1 months ago
Ultra High Performance ECC over NIST Primes on Commercial FPGAs
Elliptic Curve Cryptosystems (ECC) have gained increasing acceptance in practice due to their significantly smaller bit size of the operands compared to other public-key cryptosyst...
Tim Güneysu, Christof Paar
CGO
2003
IEEE
15 years 4 months ago
Addressing Mode Selection
Many processor architectures provide a set of addressing modes in their address generation units. For example DSPs (digital signal processors) have powerful addressing modes for e...
Erik Eckstein, Bernhard Scholz
FPL
2007
Springer
96views Hardware» more  FPL 2007»
15 years 5 months ago
Implementation of a 2-D 8x8 IDCT on the Reconfigurable Montium Core
This paper describes the mapping of a two-dimensional inverse discrete cosine transform (2-D IDCT) onto a wordlevel reconfigurable Montium R processor. This shows that the IDCT i...
Lodewijk T. Smit, Gerard K. Rauwerda, Albert Molde...