193 search results - page 32 / 39 » The TigerSHARC DSP Architecture |
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CODES
2003
IEEE
15 years 4 months ago
2003
IEEE
This paper presents a software implementation of a very fast parallel Reed-Solomon decoder on the second generation of MorphoSys reconfigurable computation platform, which is targ...
FPL
2009
Springer
15 years 3 months ago
2009
Springer
As FPGA devices become larger, more coarse-grain modules coupled with large scale reconfigurable fabric become available, thus enabling new classes of applications to run effici...
MICRO
2002
IEEE
15 years 3 months ago
2002
IEEE
Multimedia processing on embedded devices requires an architecture that leads to high performance, low power consumption, reduced design complexity, and small code size. In this p...
ICPADS
2006
IEEE
15 years 5 months ago
2006
IEEE
The widening gap between processor and memory performance is the main bottleneck for modern computer systems to achieve high processor utilization. In this paper, we propose a new...
DAC
2000
ACM
15 years 12 months ago
2000
ACM
The effect of crosstalk errors is most significant in highperformance circuits, mandating at-speed testing for crosstalk defects. This paper describes a self-test methodology that...