193 search results - page 33 / 39 » The TigerSHARC DSP Architecture |
ICASSP
2008
IEEE
15 years 5 months ago
2008
IEEE
Previous studies have shown that wireless DSP algorithms exhibit high levels of data level parallelism (DLP). Commercial and research work in the field of software defined radio...
ASPLOS
2006
ACM
15 years 5 months ago
2006
ACM
As multicore architectures enter the mainstream, there is a pressing demand for high-level programming models that can effectively map to them. Stream programming offers an attrac...
DATE
2003
IEEE
15 years 4 months ago
2003
IEEE
In this paper is described a software technique allowing to detect soft errors occurring in processor-based digital architectures. The detection mechanism is based on a set of rul...
ASAP
2005
IEEE
15 years 4 months ago
2005
IEEE
It is widely known that parallel operation execution in multiprocessor systems generates a respective increase in memory accesses. Since the memory and bus subsystems provide a li...
CODES
2005
IEEE
15 years 4 months ago
2005
IEEE
As wireless platforms converge to multimedia systems, architectures must converge to support voice, data, and video applications. From a processor architecture perspective, suppor...