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HPCA
1999
IEEE
15 years 2 months ago
Improving the Accuracy vs. Speed Tradeoff for Simulating Shared-Memory Multiprocessors with ILP Processors
Previous simulators for shared-memory architectures have imposed a large tradeoff between simulation accuracy and speed. Most such simulators model simple processors that do not e...
Murthy Durbhakula, Vijay S. Pai, Sarita V. Adve
DAC
2008
ACM
15 years 11 months ago
Parameterized timing analysis with general delay models and arbitrary variation sources
Many recent techniques for timing analysis under variability, in which delay is an explicit function of underlying parameters, may be described as parameterized timing analysis. T...
Khaled R. Heloue, Farid N. Najm
MEMOCODE
2003
IEEE
15 years 3 months ago
MoDe: A Method for System-Level Architecture Evaluation
System-level design methodologies for embedded HW/SW systems face several challenges: In order to be susceptible to systematic formal analysis based on state-space exploration, a ...
Jan Romberg, Oscar Slotosch, Gabor Hahn
DATE
2010
IEEE
157views Hardware» more  DATE 2010»
15 years 3 months ago
RMOT: Recursion in model order for task execution time estimation in a software pipeline
Abstract—This paper addresses the problem of execution time estimation for tasks in a software pipeline independent of the application structure or the underlying architecture. A...
Nabeel Iqbal, M. A. Siddique, Jörg Henkel
CCE
2004
14 years 9 months ago
Efficient short-term scheduling of refinery operations based on a continuous time formulation
The problem addressed in this work is to develop a comprehensive mathematical programming model for the efficient scheduling of oil-refinery operations. Our approach is first to d...
Zhenya Jia, Marianthi G. Ierapetritou