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» The Timely Computing Base Model and Architecture
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WSC
1997
14 years 11 months ago
Design and Implementation of HLA Time Management in the RTI Version F.0
The DoD High Level architecture (HLA) has recently become the required method for the interconnection of all DoD computer simulations. The HLA addresses the rules by which simulat...
Christopher D. Carothers, Richard Fujimoto, Richar...
ICPADS
2005
IEEE
15 years 3 months ago
An Evaluation Mechanism for QoS Management in Wireless Systems
The evaluation of QoS requirements is one of the critical functions that span both the design and the run-time phases of QoS management. This paper presents an architecture for Qo...
Behzad Bordbar, Rachid Anane, Kozo Okano
ASAP
2009
IEEE
98views Hardware» more  ASAP 2009»
14 years 7 months ago
A Power-Scalable Switch-Based Multi-processor FFT
This paper examines the architecture, algorithm and implementation of a switch-based multi-processor realization of the fast Fourier transform (FFT). The architecture employs M pr...
Bassam Jamil Mohd, Earl E. Swartzlander Jr.
MICRO
2003
IEEE
166views Hardware» more  MICRO 2003»
15 years 3 months ago
Razor: A Low-Power Pipeline Based on Circuit-Level Timing Speculation
With increasing clock frequencies and silicon integration, power aware computing has become a critical concern in the design of embedded processors and systems-on-chip. One of the...
Dan Ernst, Nam Sung Kim, Shidhartha Das, Sanjay Pa...
NIPS
2001
14 years 11 months ago
A Sequence Kernel and its Application to Speaker Recognition
A novel approach for comparing sequences of observations using an explicit-expansion kernel is demonstrated. The kernel is derived using the assumption of the independence of the ...
W. M. Campbell