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ISCAS
2005
IEEE
124views Hardware» more  ISCAS 2005»
15 years 3 months ago
Parallel FFT computation with a CDMA-based network-on-chip
— Fast Fourier transform (FFT) algorithms are used in a wide variety of digital signal processing applications and many of these require high-performance parallel implementations...
Daewook Kim, Manho Kim, Gerald E. Sobelman
ALENEX
2004
116views Algorithms» more  ALENEX 2004»
14 years 11 months ago
A Computational Framework for Handling Motion
We present a framework for implementing geometric algorithms involving motion. It is written in C++ and modeled after and makes extensive use of CGAL (Computational Geometry Algor...
Leonidas J. Guibas, Menelaos I. Karavelas, Daniel ...
CF
2004
ACM
15 years 3 months ago
The happy marriage of architecture and application in next-generation reconfigurable systems
New applications and standards are first conceived only for functional correctness and without concerns for the target architecture. The next challenge is to map them onto an arch...
Ingrid Verbauwhede, Patrick Schaumont
SIGGRAPH
1996
ACM
15 years 2 months ago
VC-1: A Scalable Graphics Computer with Virtual Local Frame Buffers
The VC-1 is a parallel graphics machine for polygon rendering based on image composition. This paper describes the architecture of the VC-1 along with a parallel polygon rendering...
Satoshi Nishimura, Tosiyasu L. Kunii
IPPS
2006
IEEE
15 years 4 months ago
A high level SoC power estimation based on IP modeling
Current electronic system design requires to be concerned with power consumption consideration. However, in a lot of design tools, the application power consumption budget is esti...
David Elléouet, Nathalie Julien, Dominique ...