4679 search results - page 72 / 936 » The Timely Computing Base Model and Architecture |
CCGRID
2006
IEEE
15 years 3 months ago
2006
IEEE
This paper focuses on architecture suitable for largescale simulation system. Based on the scenario of large-scale internet simulation, the grid technology is introduced and a new...
DAC
1997
ACM
15 years 1 months ago
1997
ACM
We present a novel technique CLIP for optimizing both the height and width of CMOS cell layouts in the two-dimensional (2D) style. CLIP is based on integer-linear programming (ILP...
DAC
2011
ACM
13 years 9 months ago
2011
ACM
This paper studies TSV-to-TSV coupling in 3D ICs. A full-chip SI analysis flow is proposed based on the proposed coupling model. Analysis results show that TSVs cause significan...
VLSID
2006
IEEE
15 years 3 months ago
2006
IEEE
This paper presents Frame Based Fair Multiprocessor Scheduler (FBFMS) which provides accurate real-time proportional fair scheduling for a set of dynamic tasks on a symmetric mult...
DAC
1994
ACM
15 years 1 months ago
1994
ACM
Sequential place and route tools for FPGAs are inherently weak at addressing both wirability and timing optimizations. This is primarily due to the difficulty in predicting these ...