1536 search results - page 103 / 308 » The Underlying Logic of Hoare Logic |
IISWC
2009
IEEE
15 years 4 months ago
2009
IEEE
—Communication traces are integral to performance modeling and analysis of parallel programs. However, execution on a large number of nodes results in a large trace volume that i...
FMCO
2007
Springer
15 years 4 months ago
2007
Springer
This article considers the coordination language Reo, a Petri net variant called zero-safe nets, and intuitionistic temporal linear logic (ITLL). The first part examines the seman...
ATS
2005
IEEE
15 years 3 months ago
2005
IEEE
— Structural transformation of a design to enhance its testability while satisfying design constraints on power and performance, can result in improved test cost and test confid...
ITC
2003
IEEE
15 years 3 months ago
2003
IEEE
In this paper, a new paradigm for designing logic circuits with concurrent error detection (CED) is described. The key idea is to exploit the asymmetric soft error susceptibility ...
TPHOL
2003
IEEE
15 years 3 months ago
2003
IEEE
MetaPRL is the latest system to come out of over twenty five years of research by the Cornell PRL group. While initially created at Cornell, MetaPRL is currently a collaborative p...