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SAC
2010
ACM
14 years 10 months ago
Efficient mapping and voltage islanding technique for energy minimization in NoC under design constraints
Voltage islanding technique in Network-on-Chip (NoC) can significantly reduce the computational energy consumption by scaling down the voltage levels of the processing elements (P...
Pavel Ghosh, Arunabha Sen
WCRE
2003
IEEE
15 years 3 months ago
An Experimentation Framework for Evaluating Disassembly and Decompilation Tools for C++ and Java
The inherent differences between C++ and Java programs dictate that the methods used for reverse engineering their compiled executables will be languagespecific. This paper looks ...
Lori Vinciguerra, Linda M. Wills, Nidhi Kejriwal, ...
DAC
2005
ACM
15 years 11 months ago
Approximate VCCs: a new characterization of multimedia workloads for system-level MpSoC design
System-level design methods specifically targeted towards multimedia applications have recently received a lot of attention. Multimedia workloads are known to have a high degree o...
Yanhong Liu, Samarjit Chakraborty, Wei Tsang Ooi
ICCAD
2008
IEEE
246views Hardware» more  ICCAD 2008»
15 years 6 months ago
MC-Sim: an efficient simulation tool for MPSoC designs
The ability to integrate diverse components such as processor cores, memories, custom hardware blocks and complex network-on-chip (NoC) communication frameworks onto a single chip...
Jason Cong, Karthik Gururaj, Guoling Han, Adam Kap...
MEMOCODE
2003
IEEE
15 years 3 months ago
LOTOS Code Generation for Model Checking of STBus Based SoC: the STBus interconnect
In the design process of SoC (System on Chip), validation is one of the most critical and costly activity. The main problem for industrial companies like STMicroelectronics, stand...
Pierre Wodey, Geoffrey Camarroque, Fabrice Baray, ...