1439 search results - page 240 / 288 » The Virtual Museum of Architecture |
VLSID
2002
IEEE
16 years 5 days ago
2002
IEEE
We describe a new algorithm for floorplan evaluation using timing-driven buffered routing according to a prescribed buffer site map. Specifically, we describe a provably good mult...
105
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HPCA
2006
IEEE
16 years 5 days ago
2006
IEEE
Previous proposals for power-aware thread-level parallelism on chip multiprocessors (CMPs) mostly focus on multiprogrammed workloads. Nonetheless, parallel computation of a single...
HPCA
2003
IEEE
16 years 5 days ago
2003
IEEE
With the scaling of technology and the need for higher performance and more functionality, power dissipation is becoming a major bottleneck for microprocessor designs. Pipeline ba...
HPCA
2002
IEEE
16 years 5 days ago
2002
IEEE
Several studies of speculative execution based on values have reported promising performance potential. However, virtually all microarchitectures in these studies were described i...
108
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HPCA
2001
IEEE
16 years 5 days ago
2001
IEEE
fipical translation lookaside buffers (TLBs)can map a far smaller region of memory than application footprints demand, and the cost of handling TLB misses therefore limits the per...