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ICMCS
2006
IEEE
113views Multimedia» more  ICMCS 2006»
15 years 3 months ago
Enhanced Architectural Support for Variable-Length Decoding
This paper proposes a new architecture for efficient variable-length decoding (VLD) of entropy-coded data for multimedia applications on general-purpose processors. It improves o...
Mohanarajah Sinnathamby, Subramania Sudharsanan, N...
PARELEC
2000
IEEE
15 years 2 months ago
Implementation of an Adaptive Reconfigurable Group Organized (ARGO) Parallel Architecture
The purpose of this paper is to demonstrate the implementation of an adaptable parallel architecture capable of system to task adaptation. The system implementation was based on X...
Lucas Szajek, Lev Kirischian
ICPR
2004
IEEE
15 years 11 months ago
An FPGA-Based Architecture for Real Time Image Feature Extraction
We propose a novel FPGA-based architecture for the extraction of four texture features using Gray Level Cooccurrence Matrix (GLCM) analysis. These features are angular second mome...
Dimitrios E. Maroulis, Dimitrios K. Iakovidis, Dim...
ISCAS
2007
IEEE
133views Hardware» more  ISCAS 2007»
15 years 4 months ago
Design of a Massively Parallel Vision Processor based on Multi-SIMD Architecture
— Increasing demands for robust image recognition systems require vision processors not only with enormous computational capacities but also with sufficient flexibility to hand...
Kota Yamaguchi, Yoshihiro Watanabe, Takashi Komuro...
FCCM
1998
IEEE
99views VLSI» more  FCCM 1998»
15 years 2 months ago
FPGA-Based Architecture Evaluation of Cryptographic Coprocessors for Smartcards
In 1996, about 600 million IC-cards were manufactured worldwide. Due to very small die sizes (max. 25 mm2 ) smartcards encounter more severe restrictions than conventional coproces...
Hagen Ploog, Dirk Timmermann