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DATE
2006
IEEE
149views Hardware» more  DATE 2006»
15 years 3 months ago
Communication architecture optimization: making the shortest path shorter in regular networks-on-chip
Network-on-Chip (NoC)-based communication represents a promising solution to complex on-chip communication problems. Due to their regular structure, mesh-like NoC architectures ha...
Ümit Y. Ogras, Radu Marculescu, Hyung Gyu Lee...
SIPS
2006
IEEE
15 years 3 months ago
Partly Parallel Overlapped Sum-Product Decoder Architectures for Quasi-Cyclic LDPC Codes
Abstract— In this paper, we propose partly parallel architectures based on optimal overlapped sum-product (OSP) decoding. To ensure high throughput and hardware utilization effi...
Ning Chen, Yongmei Dai, Zhiyuan Yan
FPL
2005
Springer
127views Hardware» more  FPL 2005»
15 years 3 months ago
Efficient Hardware Architectures for Modular Multiplication on FPGAs
The computational fundament of most public-key cryptosystems is the modular multiplication. Improving the efficiency of the modular multiplication is directly associated with the...
David Narh Amanor, Viktor Bunimov, Christof Paar, ...
IPPS
1999
IEEE
15 years 2 months ago
Plastic Cell Architecture: A Dynamically Reconfigurable Hardware-Based Computer
This paper describes a dynamically reconfigurable hardware-based computer called the Plastic Cell Architecture (PCA). PCA consists of dualstructured sea-of -cells that consist of a...
Hiroshi Nakada, Kiyoshi Oguri, Norbert Imlig, Mino...
ISCAS
1993
IEEE
133views Hardware» more  ISCAS 1993»
15 years 1 months ago
An efficient FIR filter architecture
– This paper describes an efficient architecture for FIR filters. By exploiting the reduced complexity made possible by the use of sparse powers-of-two coefficients, an FIR ...
Joseph B. Evans