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ASPDAC
2006
ACM
99views Hardware» more  ASPDAC 2006»
15 years 3 months ago
Programmable numerical function generators based on quadratic approximation: architecture and synthesis method
— This paper presents an architecture and a synthesis method for programmable numerical function generators (NFGs) for trigonometric, logarithmic, square root, and reciprocal fun...
Shinobu Nagayama, Tsutomu Sasao, Jon T. Butler
IPPS
2005
IEEE
15 years 3 months ago
Embedded MPLS Architecture
This paper presents a hardware architecture for Multi Protocol Label Switching (MPLS). MPLS is a protocol used primarily to prioritize internet traffic and improve bandwidth utili...
Raymond Peterkin, Dan Ionescu
ASAP
2006
IEEE
138views Hardware» more  ASAP 2006»
15 years 1 months ago
Configurable, High Throughput, Irregular LDPC Decoder Architecture: Tradeoff Analysis and Implementation
Low Density Parity Check (LDPC) codes are one of the best error correcting codes that enable the future generations of wireless devices to achieve higher data rates. This paper pr...
Marjan Karkooti, Predrag Radosavljevic, Joseph R. ...
FPL
2008
Springer
109views Hardware» more  FPL 2008»
14 years 11 months ago
Loop unrolling and shifting for reconfigurable architectures
Loops are an important source of optimization. In this paper, we propose an extension to our work on loop unrolling and loop shifting for reconfigurable architectures. By applying...
Ozana Silvia Dragomir, Todor Stefanov, Koen Bertel...
VLSID
2010
IEEE
190views VLSI» more  VLSID 2010»
14 years 7 months ago
A Reconfigurable Architecture for Secure Multimedia Delivery
This paper introduces a reconfigurable architecture for ensuring secure and real-time video delivery through a novel parameterized construction of the Discrete Wavelet Transform (D...
Amit Pande, Joseph Zambreno