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    JUCS
    2007
    102views more  JUCS 2007»
    The Use of Runtime Reconfiguration on FPGA Circuits to Increase the Performance of the AES Algorithm Implementation
    14 years 9 months ago
    The Use of Runtime Reconfiguration on FPGA Circuits to Increase the Performance of the AES Algorithm Implementation
    Download  www.jucs.org
    : This article presents an architecture that encrypts data with the AES algorithm. This architecture can be implemented on the Xilinx Virtex II FPGA family, by applying pipelining ...
    Oscar Pérez, Yves Berviller, Camel Tanougas...
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    FPGA
    2005
    ACM
    137views FPGA» more  FPGA 2005»
    HARP: hard-wired routing pattern FPGAs
    15 years 3 months ago
    HARP: hard-wired routing pattern FPGAs
    Download  www.ece.ucsb.edu
    Modern FPGA architectures provide ample routing resources so that designs can be routed successfully. The routing architecture is designed to handle versatile connection configur...
    Satish Sivaswamy, Gang Wang, Cristinel Ababei, Kia...
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    DATE
    2010
    IEEE
    183views Hardware» more  DATE 2010»
    Monolithically stackable hybrid FPGA
    15 years 2 months ago
    Monolithically stackable hybrid FPGA
    Download  www.date-conference.com
    — The paper introduces novel field programmable gate array (FPGA) circuits based on hybrid CMOS/resistive switching device (memristor) technology and explores several logic archi...
    Dmitri Strukov, Alan Mishchenko
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    FPGA
    2008
    ACM
    163views FPGA» more  FPGA 2008»
    TORCH: a design tool for routing channel segmentation in FPGAs
    14 years 11 months ago
    TORCH: a design tool for routing channel segmentation in FPGAs
    Download  www-isl.stanford.edu
    A design tool for routing channel segmentation in islandstyle FPGAs is presented. Given the FPGA architecture parameters and a set of benchmark designs, the tool optimizes routing...
    Mingjie Lin, Abbas El Gamal
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    DAC
    2007
    ACM
    96views Computer Architecture» more  DAC 2007»
    Using Negative Edge Triggered FFs to Reduce Glitching Power in FPGA Circuits
    15 years 10 months ago
    Using Negative Edge Triggered FFs to Reduce Glitching Power in FPGA Circuits
    Download  www.eecg.toronto.edu
    Tomasz S. Czajkowski, Stephen Dean Brown
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