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IPPS
2003
IEEE
15 years 3 months ago
Leveraging Block Decisions and Aggregation in the ShareStreams QoS Architecture
ShareStreams (Scalable Hardware Architectures for Stream Schedulers) is a canonical architecture for realizing a range of scheduling disciplines. This paper discusses the design c...
Raj Krishnamurthy, Sudhakar Yalamanchili, Karsten ...
CODES
2007
IEEE
15 years 4 months ago
Secure FPGA circuits using controlled placement and routing
In current Field-Programmable-Logic Architecture (FPGA) design flows, it is very hard to control the routing of submodules. It is thus very hard to make an identical copy of an ex...
Pengyuan Yu, Patrick Schaumont
AIA
2006
14 years 11 months ago
FPGA-Targeted Neural Architecture for Embedded Alertness Detection
Several recent works have used neural networks to discriminate vigilance states in humans from electroencephalographic (EEG) signals. Our study aims at being more exhaustive. It t...
Bernard Girau, Khaled Ben Khalifa
ISCAS
2005
IEEE
153views Hardware» more  ISCAS 2005»
15 years 3 months ago
A RAM-based FPGA implementation of the 64-bit MISTY1 block cipher
—A high-throughput hardware architecture and FPGA implementation of the 64-bit NESSIE proposal, MISTY1 block cipher, is presented in this paper. This architecture, in contrast to...
Paris Kitsos, Michalis D. Galanis, Odysseas G. Kou...
FPL
2005
Springer
96views Hardware» more  FPL 2005»
15 years 3 months ago
An Integrated Framework for Architecture Level Exploration of Reconfigurable Platform
In this paper, the EX-VPR tool, which used for architecture level exploration, is presented. This tool belongs to an integrated framework (MEANDER) for mapping applications into a...
K. Siozios, Konstantinos Tatas, George Koutroumpez...