Sciweavers

862 search results - page 44 / 173
» The amorphous FPGA architecture
Sort
View
DAC
2006
ACM
15 years 10 months ago
Architecture-aware FPGA placement using metric embedding
Since performance on FPGAs is dominated by the routing architecture rather than wirelength, we propose a new architecture-aware approach to initial FPGA placement that models the ...
Padmini Gopalakrishnan, Xin Li, Lawrence T. Pilegg...
SLIP
2005
ACM
15 years 3 months ago
A 3-D FPGA wire resource prediction model validated using a 3-D placement and routing tool
The interconnection architecture of FPGAs such as switches dominates performance of FPGAs. Three-dimensional integration of FPGAs overcomes interconnect limitations by allowing in...
Young-Su Kwon, Payam Lajevardi, Anantha P. Chandra...
ARC
2010
Springer
178views Hardware» more  ARC 2010»
15 years 4 months ago
An Analysis of Delay Based PUF Implementations on FPGA
Physical Unclonable Functions promise cheap, efficient, and secure identification and authentication of devices. In FPGA devices, PUFs may be instantiated directly from FPGA fabri...
Sergey Morozov, Abhranil Maiti, Patrick Schaumont
ICES
1998
Springer
131views Hardware» more  ICES 1998»
15 years 2 months ago
Aspects of Digital Evolution: Geometry and Learning
In this paper we present a new chromosome representation for evolving digital circuits. The representation is based very closely on the chip architecture of the Xilinx 6216 FPGA. W...
Julian F. Miller, Peter Thomson
DAC
1993
ACM
15 years 1 months ago
A Negative Reinforcement Method for PGA Routing
We present an efficient and effective method for the detailed routing of symmetrical or sea-of-gates FPGA architectures. Instead of breaking the problem into 2-terminal net collec...
Forbes D. Lewis, Wang Chia-Chi Pong