Heterogeneous or co-processor architectures are becoming an important component of high productivity computing systems (HPCS). In this work the performance of a GPU based HPCS is c...
David Huw Jones, Adam Powell, Christos-Savvas Boug...
Automated code generation and performance tuning techniques for concurrent architectures such as GPUs, Cell and FPGAs can provide integer factor speedups over multi-core processor...
This paper proposes an FPGA implementation of an Adaptive Noise Canceller using the Least Mean Square (LMS) algorithm. The hardware architecture is synthesized using the Xilinx Sp...
The CLA-EC is a model obtained by combining the concepts of cellular learning automata and evolutionary algorithms. The parallel structure of the CLA-EC makes it suitable for hard...
Abstract-The network on chip will become a future general purpose interconnect for FPGAs much like today's standard OPB or PLB bus architectures. However, performance characte...