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ASAP
2009
IEEE
159views Hardware» more  ASAP 2009»
15 years 4 months ago
A High-Performance Hardware Architecture for Spectral Hash Algorithm
—The Spectral Hash algorithm is one of the Round 1 candidates for the SHA-3 family, and is based on spectral arithmetic over a finite field, involving multidimensional discrete...
Ray C. C. Cheung, Çetin K. Koç, John...
DSD
2008
IEEE
121views Hardware» more  DSD 2008»
15 years 4 months ago
A Parallel and Modular Architecture for 802.16e LDPC Codes
We propose a parallel and modular architecture well suited to 802.16e WiMax LDPC code decoding. The proposed design is fully compliant with all the code classes defined by the Wi...
François Charot, Christophe Wolinski, Nicol...
MSE
2003
IEEE
97views Hardware» more  MSE 2003»
15 years 3 months ago
Harnessing FPGAs for Computer Architecture Education
Computer architecture is often taught by having students use software to design and simulate individual pieces of a computer processor. We have developed a method that will take t...
Mark Holland, James Harris, Scott Hauck
ARC
2007
Springer
169views Hardware» more  ARC 2007»
15 years 4 months ago
Designing Heterogeneous FPGAs with Multiple SBs
Abstract. The novel design of high-speed and low-energy FPGA routing architecture consisting of appropriate wire segments and multiple Switch Boxes is introduced. For that purpose,...
Kostas Siozios, Stelios Mamagkakis, Dimitrios Soud...
FCCM
1998
IEEE
149views VLSI» more  FCCM 1998»
15 years 2 months ago
Configuration Compression for the Xilinx XC6200 FPGA
One of the major overheads in reconfigurable computing is the time it takes to reconfigure the devices in the system. This overhead limits the speedups possible in this exciting n...
Scott Hauck, Zhiyuan Li, Eric J. Schwabe