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FCCM
2004
IEEE
91views VLSI» more  FCCM 2004»
15 years 1 months ago
An FPGA Interpolation Processor for Soft-Decision Reed-Solomon Decoding
We propose a parallel architecture for implementing the interpolation step in the Koetter-Vardy soft-decision ReedSolomon decoding algorithm. The key feature is the embedding of b...
Warren J. Gross, Frank R. Kschischang, P. Glenn Gu...
DAC
2001
ACM
15 years 10 months ago
Performance-Driven Multi-Level Clustering with Application to Hierarchical FPGA Mapping
In this paper, we study the problem of performance-driven multi-level circuit clustering with application to hierarchical FPGA designs. We first show that the performance-driven m...
Jason Cong, Michail Romesis
FPL
2009
Springer
156views Hardware» more  FPL 2009»
15 years 2 months ago
A highly scalable Restricted Boltzmann Machine FPGA implementation
Restricted Boltzmann Machines (RBMs) — the building block for newly popular Deep Belief Networks (DBNs) — are a promising new tool for machine learning practitioners. However,...
Sang Kyun Kim, Lawrence C. McAfee, Peter L. McMaho...
FPGA
1999
ACM
174views FPGA» more  FPGA 1999»
15 years 2 months ago
Reduction of Latency and Resource Usage in Bit-Level Pipelined Data Paths for FPGAs
Pipelining of data path structures increases the throughput rate at the expense of enlarged resource usage and latency unless architectures optimized towards specific applications...
Peter Kollig, Bashir M. Al-Hashimi
DAC
2008
ACM
15 years 10 months ago
TuneFPGA: post-silicon tuning of dual-Vdd FPGAs
Modern CMOS manufacturing processes have significant variability, which necessitates guard banding to achieve reasonable yield. We study an FPGA architecture with a dual voltage s...
Stephen Bijansky, Adnan Aziz