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FPGA
2010
ACM
232views FPGA» more  FPGA 2010»
14 years 10 months ago
High-throughput bayesian computing machine with reconfigurable hardware
We use reconfigurable hardware to construct a high throughput Bayesian computing machine (BCM) capable of evaluating probabilistic networks with arbitrary DAG (directed acyclic gr...
Mingjie Lin, Ilia Lebedev, John Wawrzynek
CAMP
2005
IEEE
15 years 3 months ago
Parallel Extraction Architecture for Image Moments of Numerous Objects
— In this paper, we propose a new architecture that can extract information of numerous objects in an image at highspeed. Various characteristics can be obtained from the image m...
Yoshihiro Watanabe, Takashi Komuro, Shingo Kagami,...
ERSA
2009
147views Hardware» more  ERSA 2009»
14 years 7 months ago
Fault Avoidance in Medium-Grain Reconfigurable Hardware Architectures
Medium-grain reconfigurable hardware (MGRH) architectures represent a hybrid between the versatility of a field programmable gate array (FPGA) and the computational power of a cust...
Kylan Robinson, José G. Delgado-Frias
FCCM
2009
IEEE
171views VLSI» more  FCCM 2009»
15 years 4 months ago
Accelerating SPICE Model-Evaluation using FPGAs
—Single-FPGA spatial implementations can provide an order of magnitude speedup over sequential microprocessor implementations for data-parallel, floating-point computation in SP...
Nachiket Kapre, André DeHon
FPGA
2004
ACM
158views FPGA» more  FPGA 2004»
15 years 3 months ago
A novel coarse-grain reconfigurable data-path for accelerating DSP kernels
In this paper, an efficient implementation of a high performance coarse-grain reconfigurable data-path on a mixed-granularity reconfigurable platform is presented. It consists of ...
Michalis D. Galanis, George Theodoridis, Spyros Tr...