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» The art of multiprocessor programming
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DATE
2009
IEEE
103views Hardware» more  DATE 2009»
15 years 3 months ago
Fault-tolerant average execution time optimization for general-purpose multi-processor system-on-chips
1 Fault-tolerance is due to the semiconductor technology development important, not only for safety-critical systems but also for general-purpose (non-safety critical) systems. How...
Mikael Väyrynen, Virendra Singh, Erik Larsson
ISCA
1995
IEEE
147views Hardware» more  ISCA 1995»
15 years 3 months ago
Dynamic Self-Invalidation: Reducing Coherence Overhead in Shared-Memory Multiprocessors
This paper introduces dynamic self-invalidation (DSI), a new technique for reducing cache coherence overhead in shared-memory multiprocessors. DSI eliminates invalidation messages...
Alvin R. Lebeck, David A. Wood
ERSA
2007
177views Hardware» more  ERSA 2007»
15 years 1 months ago
Energy-Aware System Synthesis for Reconfigurable Chip Multiprocessors
- Even though state-of-the-art FPGAs present new opportunities in exploring low-cost high-performance architectures for floating-point scientific applications, they also pose serio...
Xiaofang Wang, Sotirios G. Ziavras, Jie Hu
JISE
2002
165views more  JISE 2002»
14 years 11 months ago
Locality-Preserving Dynamic Load Balancing for Data-Parallel Applications on Distributed-Memory Multiprocessors
Load balancing and data locality are the two most important factors in the performance of parallel programs on distributed-memory multiprocessors. A good balancing scheme should e...
Pangfeng Liu, Jan-Jan Wu, Chih-Hsuae Yang
CAL
2010
14 years 9 months ago
A Dynamic Pressure-Aware Associative Placement Strategy for Large Scale Chip Multiprocessors
This paper describes dynamic pressure-aware associative placement (DPAP), a novel distributed cache management scheme for large-scale chip multiprocessors. Our work is motivated by...
Mohammad Hammoud, Sangyeun Cho, Rami G. Melhem