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DSD
2010
IEEE
172views Hardware» more  DSD 2010»
13 years 6 months ago
Adaptive Cache Memories for SMT Processors
Abstract—Resizable caches can trade-off capacity for access speed to dynamically match the needs of the workload. In Simultaneous Multi-Threaded (SMT) cores, the caching needs ca...
Sonia López, Oscar Garnica, David H. Albone...
ESA
2008
Springer
159views Algorithms» more  ESA 2008»
13 years 8 months ago
Cache-Oblivious Red-Blue Line Segment Intersection
We present an optimal cache-oblivious algorithm for finding all intersections between a set of non-intersecting red segments and a set of non-intersecting blue segments in the plan...
Lars Arge, Thomas Mølhave, Norbert Zeh
CORR
2008
Springer
120views Education» more  CORR 2008»
13 years 6 months ago
Cache-Oblivious Selection in Sorted X+Y Matrices
Let X[0..n - 1] and Y [0..m - 1] be two sorted arrays, and define the m
Mark de Berg, Shripad Thite
IPPS
2010
IEEE
13 years 4 months ago
Exploiting inter-thread temporal locality for chip multithreading
Multi-core organizations increasingly support multiple threads per core. Threads on a core usually share a single first-level data cache, so thread schedulers must try to minimize ...
Jiayuan Meng, Jeremy W. Sheaffer, Kevin Skadron