56 search results - page 4 / 12 » The chained-cubic tree interconnection network |
ICCAD
2003
IEEE
15 years 6 months ago
2003
IEEE
The Y-architecture for on-chip interconnect is based on pervasive use of 0-, 120-, and 240-degree oriented semi-global and global wiring. Its use of three uniform directions explo...
ICCAD
2006
IEEE
15 years 6 months ago
2006
IEEE
This paper presents a new Multilevel hierarchical FPGA (MFPGA) architecture that unifies two unidirectional programmable networks: A predictible downward network based on the But...
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HPCC
2007
Springer
15 years 1 months ago
2007
Springer
Abstract. Nowadays, power consumption reduction techniques are being increasingly used in computer systems, and high-performance computing systems are not an exception. In particul...
68
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FPGA
2003
ACM
15 years 2 months ago
2003
ACM
How does multilevel metalization impact the design of FPGA interconnect? The availability of a growing number of metal layers presents the opportunity to use wiring in the thirddi...
SLIP
2003
ACM
15 years 2 months ago
2003
ACM
The problem of interconnect architecture arises when an array of processors needs to be integrated on one chip. With the deep sub-micron technology, devices become cheap while wir...