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ISCA
1996
IEEE
130views Hardware» more  ISCA 1996»
15 years 7 months ago
Informing Memory Operations: Providing Memory Performance Feedback in Modern Processors
Memory latency is an important bottleneck in system performance that cannot be adequately solved by hardware alone. Several promising software techniques have been shown to addres...
Mark Horowitz, Margaret Martonosi, Todd C. Mowry, ...
PLDI
1996
ACM
15 years 7 months ago
Realistic Compilation by Partial Evaluation
Two key steps in the compilation of strict functional languages are the conversion of higher-order functions to data structures (closures) and the transformation to tail-recursive...
Michael Sperber, Peter Thiemann
SIGSOFT
1996
ACM
15 years 7 months ago
Tool Support for Planning the Restructuring of Data Abstractions in Large Systems
Abstractions in Large Systems William G. Griswold, Member, IEEE, Morison I. Chen, Robert W. Bowdidge, Jenny L. Cabaniss, Van B. Nguyen, and J. David Morgenthaler Restructuring soft...
William G. Griswold, Morison I. Chen, Robert W. Bo...
EURODAC
1994
IEEE
209views VHDL» more  EURODAC 1994»
15 years 7 months ago
MOS VLSI circuit simulation by hardware accelerator using semi-natural models
- The accelerator is destined to circuit-level simulation of digital and analog/digital MOS VLSI'c containing of up to 100 thousand transistors (with 16 Mb RAM host-machine). ...
Victor V. Denisenko
PDIS
1993
IEEE
15 years 7 months ago
Log-Based Directory Resolution in the Coda File System
semantic knowledge all concurrent partitionedAbstract updates to an object must be treated as conflicting, andOptimistic replication is an important technique for merged manually b...
Puneet Kumar, Mahadev Satyanarayanan
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