517 search results - page 48 / 104 » The design of a low energy FPGA |
ICCD
2004
IEEE
15 years 8 months ago
2004
IEEE
This paper proposes a power-aware cache block allocation algorithm for the way-selective setassociative cache on embedded systems to reduce energy consumption without additional d...
103
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NOCS
2008
IEEE
15 years 6 months ago
2008
IEEE
In this paper, we introduce the use of slow-silent virtual channels to reduce the switching power of on-chip networks while keeping the leakage power small. Adding virtual channel...
ISLPED
2003
ACM
15 years 5 months ago
2003
ACM
Distributed wireless ad-hoc networks (DWANs) pose numerous technical challenges. Among them, two are widely considered as crucial: autonomous localized operation and minimization ...
85
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DAC
2002
ACM
16 years 24 days ago
2002
ACM
An architectural solution to reducing memory energy consumption is to adopt a multi-bank memory system instead of a monolithic (single-bank) memory system. Some recent multi-bank ...
ISLPED
2004
ACM
15 years 5 months ago
2004
ACM
As clock frequency and die area increase, achieving energy efficiency, while distributing a low skew, global clock signal becomes increasingly difficult. Challenges imposed by dee...