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» The design of a low energy FPGA
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ISCAS
2003
IEEE
139views Hardware» more  ISCAS 2003»
15 years 3 months ago
Development of an AA size energy transducer with micro resonators
This paper presents the preliminary design and experimental results of a standard AA size vibration-induced micro energy transducer which is integrated with a power-management cir...
Johnny M. H. Lee, Steve C. L. Yuen, Wen J. Li, Phi...
AINA
2009
IEEE
15 years 4 months ago
An Energy Efficient Chain-Based Clustering Routing Protocol for Wireless Sensor Networks
— Wireless sensor network consisting of a large number of sensors is effective for gathering data in a variety of environments. Since the sensors operate on battery of limited po...
Jae Duck Yu, Kyung Tae Kim, Bo Yle Jung, Hee Yong ...
ISLPED
2010
ACM
128views Hardware» more  ISLPED 2010»
14 years 7 months ago
Rank-aware cache replacement and write buffering to improve DRAM energy efficiency
DRAM power and energy efficiency considerations are becoming increasingly important for low-power and mobile systems. Using lower power modes provided by commodity DRAM chips redu...
Ahmed M. Amin, Zeshan Chishti
ICUMT
2009
14 years 7 months ago
On the adaptivity of today's Energy-Efficient MAC protocols under varying traffic conditions
Energy efficiency is a major concern in the design of Wireless Sensor Networks (WSNs) and their communication protocols. As the radio transceiver typically accounts for a major por...
Philipp Hurni, Torsten Braun
ISVLSI
2008
IEEE
158views VLSI» more  ISVLSI 2008»
15 years 4 months ago
Improving Energy Efficiency of Configurable Caches via Temperature-Aware Configuration Selection
Active power used to be the primary contributor to total power dissipation of CMOS designs, but with the technology scaling, the share of leakage in total power consumption of dig...
Hamid Noori, Maziar Goudarzi, Koji Inoue, Kazuaki ...