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» The design of a low power asynchronous multiplier
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ICCD
2008
IEEE
165views Hardware» more  ICCD 2008»
14 years 3 months ago
Analysis and minimization of practical energy in 45nm subthreshold logic circuits
Abstract— Over the last decade, the design of ultra-lowpower digital circuits in subthreshold regime has been driven by the quest for minimum energy per operation. In this contri...
David Bol, Renaud Ambroise, Denis Flandre, Jean-Di...
PRDC
2000
IEEE
13 years 10 months ago
Enforcing synchronous system properties on top of timed systems
A synchronous system model is a simple yet powerful distributed system model that reduces the complexity of the design and implementation of dependable distributed applications. H...
Christof Fetzer
OSDI
1994
ACM
13 years 7 months ago
Storage Alternatives for Mobile Computers
Mobile computers such as notebooks, subnotebooks, and palmtops require low weight, low power consumption, and good interactive performance. These requirements impose many challeng...
Fred Douglis, Ramón Cáceres, M. Fran...
DSD
2005
IEEE
116views Hardware» more  DSD 2005»
13 years 12 months ago
Optimization of a Bus-based Test Data Transportation Mechanism in System-on-Chip
The increasing amount of test data needed to test SOC (System-on-Chip) entails efficient design of the TAM (test access mechanism), which is used to transport test data inside the...
Anders Larsson, Erik Larsson, Petru Eles, Zebo Pen...
MVA
2007
196views Computer Vision» more  MVA 2007»
13 years 7 months ago
Fingerprint Verification Using Perturbation Method
This paper describes a new, powerful technique of fingerprint verification based on a perturbation method. The proposed method consists of four parts. The first part performs loca...
Satoshi Otaka, Yoshihisa Nishiyama, Takahiro Hatan...