72 search results - page 3 / 15 » The design of a low power asynchronous multiplier |
JOLPE
2008
13 years 6 months ago
2008
CDES
2006
13 years 7 months ago
2006
In this paper, a double precision IEEE 754 floating-point multiplier with high speed and low power is presented. The bottleneck of any double precision floatingpoint multiplier des...
KES
2005
Springer
13 years 11 months ago
2005
Springer
Abstract. An energy-efficient power-aware design is highly desirable for digital signal processing functions that encounter a wide diversity of operating scenarios in battery-power...
HPCC
2007
Springer
14 years 13 days ago
2007
Springer
Abstract. Low-power design became crucial with the widespread use of the embedded systems, where a small battery has to last for a long period. The embedded processors need to ef...
ISLPED
2000
ACM
13 years 10 months ago
2000
ACM
In this paper, we describe area and power reduction techniques for a low-latency adaptive finite-impulse response filter for magnetic recording read channel applications. Variou...