In this paper we present a high-performance, high throughput, and area efficient architecture for the VLSI implementation of the AES algorithm. The subkeys, required for each round...
Naga M. Kosaraju, Murali R. Varanasi, Saraju P. Mo...
The IA-64 architecture defers floating point and integer division to software. To ensure correctness and maximum efficiency, Intel provides a number of recommended algorithms which...
We present an efficient coarse grained parallel algorithm for computing a maximum weight matching in trees. A divide and conquer approach based on centroid decomposition of trees ...
This document formalizes and discusses the implementation of a new, more efficient probabilistic plan recognition algorithm called Yet Another Probabilistic Plan Recognizer, (Yapp...
Christopher W. Geib, John Maraist, Robert P. Goldm...
ABR was standardised by the ATM Forum in 1996 . Source, destination and switch behaviours were specified. However, a lot of freedom was left to the switch manufacturers to impleme...