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DATE
2004
IEEE
154views Hardware» more  DATE 2004»
15 years 10 months ago
Fast Exploration of Parameterized Bus Architecture for Communication-Centric SoC Design
For successful SoC design, efficient and scalable communication architecture is crucial. Some bus interconnects now provide configurable structures to meet this requirement of an ...
Chulho Shin, Young-Taek Kim, Eui-Young Chung, Kyu-...
DATE
2004
IEEE
123views Hardware» more  DATE 2004»
15 years 10 months ago
Synthesis and Optimization of Threshold Logic Networks with Application to Nanotechnologies
We propose an algorithm for efficient threshold network synthesis of arbitrary multi-output Boolean functions. The main purpose of this work is to bridge the wide gap that currentl...
Rui Zhang, Pallav Gupta, Lin Zhong, Niraj K. Jha
CC
2006
Springer
182views System Software» more  CC 2006»
15 years 10 months ago
Selective Runtime Memory Disambiguation in a Dynamic Binary Translator
Abstract. Alias analysis, traditionally performed statically, is unsuited for a dynamic binary translator (DBT) due to incomplete control-flow information and the high complexity o...
Bolei Guo, Youfeng Wu, Cheng Wang, Matthew J. Brid...
DSRT
2004
IEEE
15 years 10 months ago
HLA-Based Distributed Simulation Cloning
Distributed simulation cloning technology is designed to analyze alternative scenarios of a distributed simulation concurrently within the same execution session. The goal is to o...
Dan Chen, Stephen John Turner, Boon-Ping Gan, Went...
CGO
2006
IEEE
15 years 10 months ago
Compiler Optimizations to Reduce Security Overhead
In this work, we present several compiler optimizations to reduce the overhead due to software protection. We first propose an aggressive rematerialization algorithm which attempt...
Tao Zhang, Xiaotong Zhuang, Santosh Pande
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