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INTERACTIONS
2010
92views more  INTERACTIONS 2010»
14 years 9 months ago
PUX: patterns of user experience
s from a concrete to a new abstract level of description [1]. Rises in abstraction level happen regularly in all fields, but the key difference in Alexander's work was that ra...
Alan F. Blackwell, Sally Fincher
TC
2010
14 years 6 months ago
Performance Comparison of Graphics Processors to Reconfigurable Logic: A Case Study
A systematic approach to the comparison of the graphics processor (GPU) and reconfigurable logic is defined in terms of three throughput drivers. The approach is applied to five ca...
Ben Cope, Peter Y. K. Cheung, Wayne Luk, Lee W. Ho...
TII
2010
146views Education» more  TII 2010»
14 years 6 months ago
A Flexible Design Flow for Software IP Binding in FPGA
Software intellectual property (SWIP) is a critical component of increasingly complex field programmable gate arrays (FPGA)-based system-on-chip (SOC) designs. As a result, develop...
Michael A. Gora, Abhranil Maiti, Patrick Schaumont
DAC
2004
ACM
16 years 21 days ago
Virtual memory window for application-specific reconfigurable coprocessors
Reconfigurable Systems-on-Chip (SoCs) on the market consist of full-fledged processors and large Field-Programmable Gate-Arrays (FPGAs). The latter can be used to implement the sy...
Miljan Vuletic, Laura Pozzi, Paolo Ienne
DAC
2006
ACM
16 years 21 days ago
Simultaneous time slack budgeting and retiming for dual-Vdd FPGA power reduction
Field programmable dual-Vdd interconnects are effective to reduce FPGA power. Assuming uniform length interconnects, existing work has developed time slack budgeting to minimize p...
Yu Hu, Yan Lin, Lei He, Tim Tuan