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MICRO
2002
IEEE
143views Hardware» more  MICRO 2002»
15 years 9 months ago
Effective instruction scheduling techniques for an interleaved cache clustered VLIW processor
Clustering is a common technique to overcome the wire delay problem incurred by the evolution of technology. Fully-distributed architectures, where the register file, the functio...
Enric Gibert, F. Jesús Sánchez, Anto...
MICRO
2002
IEEE
164views Hardware» more  MICRO 2002»
15 years 9 months ago
A quantitative framework for automated pre-execution thread selection
Pre-execution attacks cache misses for which conventional address-prediction driven prefetching is ineffective. In pre-execution, copies of cache miss computations are isolated fr...
Amir Roth, Gurindar S. Sohi
ICPP
1999
IEEE
15 years 8 months ago
A Bandwidth-Efficient Implementation of Mesh with Multiple Broadcasting
This paper presents a mesh with virtual buses as the bandwidth-efficient implementation of the mesh with multiple broadcasting on which many computational problems can be solved w...
Jong Hyuk Choi, Bong Wan Kim, Kyu Ho Park, Kwang-I...
ISCA
1996
IEEE
130views Hardware» more  ISCA 1996»
15 years 8 months ago
Informing Memory Operations: Providing Memory Performance Feedback in Modern Processors
Memory latency is an important bottleneck in system performance that cannot be adequately solved by hardware alone. Several promising software techniques have been shown to addres...
Mark Horowitz, Margaret Martonosi, Todd C. Mowry, ...
ISCA
1993
IEEE
117views Hardware» more  ISCA 1993»
15 years 8 months ago
Evaluation of Release Consistent Software Distributed Shared Memory on Emerging Network Technology
We evaluate the e ect of processor speed, network bandwidth, and software overhead on the performance of release-consistent software distributed shared memory. We examine ve di er...
Sandhya Dwarkadas, Peter J. Keleher, Alan L. Cox, ...