3192 search results - page 425 / 639 » The minimum latency problem |
127
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DATE
2004
IEEE
15 years 7 months ago
2004
IEEE
A challenge facing designers of systems on chip (SoC) containing networks on chip (NoC) is to find NoC instances that balance the cost (e.g. area) and performance (e.g. latency an...
138
Voted
EUC
2006
Springer
15 years 7 months ago
2006
Springer
Abstract. Well-scheduled communications, in conjunction with the aggregation of data reduce the energy waste on idle listening and redundant transmissions. In addition, the adjusta...
143
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CASES
2001
ACM
15 years 7 months ago
2001
ACM
With the widening performance gap between processors and main memory, efficient memory accessing behavior is necessary for good program performance. Loop partition is an effective...
125
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CGO
2003
IEEE
15 years 7 months ago
2003
IEEE
In this paper, we present METRIC, an environment for determining memory inefficiencies by examining data traces. METRIC is designed to alter the performance behavior of applicatio...
157
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EUROPAR
2000
Springer
15 years 7 months ago
2000
Springer
Abstract. Definitions for the uniform representation of d-dimensional matrices serially in Morton-order (or Z-order) support both their use with cartesian indices, and their divide...