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ISCA
2000
IEEE
121views Hardware» more  ISCA 2000»
15 years 8 months ago
Memory access scheduling
The bandwidth and latency of a memory system are strongly dependent on the manner in which accesses interact with the “3-D” structure of banks, rows, and columns characteristi...
Scott Rixner, William J. Dally, Ujval J. Kapasi, P...
DOLAP
2000
ACM
15 years 8 months ago
Comparing Nested GPSJ Queries in Multidimensional Databases
A multidimensional database can be seen as a collection of multidimensional cubes, from which information is usually extracted by aggregation; aggregated data can be calculated ei...
Matteo Golfarelli, Stefano Rizzi
FOCS
1998
IEEE
15 years 8 months ago
Jitter Control in QoS Networks
We study jitter control in networks with guaranteed quality of service (QoS) from the competitive analysis point of view: we propose on-line algorithms that control jitter and comp...
Yishay Mansour, Boaz Patt-Shamir
LCTRTS
1999
Springer
15 years 8 months ago
Effective Exploitation of a Zero Overhead Loop Buffer
A Zero Overhead Loop Buffer (ZOLB) is an architectural feature that is commonly found in DSP processors. This buffer can be viewed as a compiler managed cache that contains a sequ...
Gang-Ryung Uh, Yuhong Wang, David B. Whalley, Sanj...
127
Voted
SIGGRAPH
1990
ACM
15 years 8 months ago
Reusable motion synthesis using state-space controllers
The use of physically-based techniques for computer animation can result in realistic object motion. The price paid for physically-based motion synthesis lies in increased computa...
Michiel van de Panne, Eugene Fiume, Zvonko G. Vran...