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» The performance of circuit switching in the internet
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GLVLSI
2005
IEEE
147views VLSI» more  GLVLSI 2005»
15 years 3 months ago
1-V 7-mW dual-band fast-locked frequency synthesizer
This paper presents a fully integrated 1-V, dual band, fastlocked frequency synthesizer for IEEE 802.11 a/b/g WLAN applications. It can synthesize frequencies in the range of 2.4 ...
Vikas Sharma, Chien-Liang Chen, Chung-Ping Chen
DATE
2000
IEEE
114views Hardware» more  DATE 2000»
15 years 1 months ago
Automating RT-Level Operand Isolation to Minimize Power Consumption in Datapaths
Designs which do not fully utilize their arithmetic datapath components typically exhibit a significant overhead in power consumption. Whenever a module performs an operation who...
Michael Münch, Norbert Wehn, Bernd Wurth, Ren...
ASPDAC
2007
ACM
121views Hardware» more  ASPDAC 2007»
15 years 1 months ago
Timing-Aware Decoupling Capacitance Allocation in Power Distribution Networks
Power supply noise increases the circuit delay, which may lead to performance failure of a design. Decoupling capacitance (decap) addition is effective in reducing the power suppl...
Sanjay Pant, David Blaauw
CNSR
2010
IEEE
164views Communications» more  CNSR 2010»
15 years 27 days ago
Buffered Crossbar Fabrics Based on Networks on Chip
— Buffered crossbar (CICQ) switches have shown a high potential in scaling Internet routers capacity. However, they require expensive on-chip buffers whose cost grows quadratical...
Lotfi Mhamdi, Kees Goossens, Iria Varela Senin
TPDS
2002
142views more  TPDS 2002»
14 years 9 months ago
MediaWorm: A QoS Capable Router Architecture for Clusters
With the increasing use of clusters in real-time applications, it has become essential to design high performance networks with Quality-of-ServiceQoS guarantees. In this paper, we...
Ki Hwan Yum, Eun Jung Kim, Chita R. Das, Aniruddha...