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» The performance of circuit switching in the internet
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ANCS
2006
ACM
15 years 3 months ago
A practical fast parallel routing architecture for Clos networks
Clos networks are an important class of switching networks due to their modular structure and much lower cost compared with crossbars. For routing I/O permutations of Clos network...
Si-Qing Zheng, Ashwin Gumaste, Enyue Lu
BROADNETS
2005
IEEE
15 years 3 months ago
Network design for IP-centric light trail networks
Abstract— We explore network design principles for nextgeneration all-optical wide-area networks, employing light-trail technology. Light-trail [1] is a light-wave circuit that a...
Srivatsan Balasubramanian, Ahmed E. Kamal, Arun K....
ICCAD
2006
IEEE
132views Hardware» more  ICCAD 2006»
15 years 3 months ago
Clock buffer polarity assignment for power noise reduction
Abstract—Power/ground noise is a major source of VLSI circuit timing variations. This work aims to reduce clock network induced power noise by assigning different signal polariti...
Rupak Samanta, Ganesh Venkataraman, Jiang Hu
ISCAS
2005
IEEE
185views Hardware» more  ISCAS 2005»
15 years 3 months ago
2 GHz 8-bit CMOS ROM-less direct digital frequency synthesizer
—This paper presents a 2GHz 8-bit CMOS ROM-less direct digital frequency synthesizer (DDFS). Nonlinear current steering digital to analog converter (DAC) has been utilized to con...
Xuefeng Yu, Foster F. Dai, Yin Shi, Ronghua Zhu
DFT
2002
IEEE
103views VLSI» more  DFT 2002»
15 years 2 months ago
Input Ordering in Concurrent Checkers to Reduce Power Consumption
A novel approach for reducing power consumption in checkers used for concurrent error detection is presented. Spatial correlations between the outputs of the circuit that drives t...
Kartik Mohanram, Nur A. Touba