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MICRO
2002
IEEE
131views Hardware» more  MICRO 2002»
14 years 9 months ago
Protocol Wrappers for Layered Network Packet Processing in Reconfigurable Hardware
abstracting the operation of lower-level packet processing functions. The library synthesizes into field-programmable gate array (FPGA) logic and is utilized in a network platform ...
Florian Braun, John W. Lockwood, Marcel Waldvogel
GLVLSI
2009
IEEE
189views VLSI» more  GLVLSI 2009»
15 years 4 months ago
High-performance, cost-effective heterogeneous 3D FPGA architectures
In this paper, we propose novel architectural and design techniques for three-dimensional field-programmable gate arrays (3D FPGAs) with Through-Silicon Vias (TSVs). We develop a...
Roto Le, Sherief Reda, R. Iris Bahar
IMC
2006
ACM
15 years 3 months ago
BGP convergence in virtual private networks
Multi-protocol label switching (MPLS) virtual private networks (VPNs) have had significant and growing commercial deployments. In this paper we present the first systematic stud...
Dan Pei, Jacobus E. van der Merwe
ISCC
2000
IEEE
118views Communications» more  ISCC 2000»
15 years 1 months ago
Differentiated Services and Integrated Services Use of MPLS
All the new emerging QoS service architectures are motivated by the desire to improve the overall performance of IP networks. Integrated Services (Intserv), Differentiated Service...
Eric Horlait, Nicolas Rouhana
CN
1998
66views more  CN 1998»
14 years 9 months ago
Route Servers for Inter-Domain Routing
Internet transmission and switching facilities are partitioned into different administrative domains. To effect routing between domains, domain border routers establish pairwise p...
Ramesh Govindan, Cengiz Alaettinoglu, Kannan Varad...