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RECONFIG
2008
IEEE
225views VLSI» more  RECONFIG 2008»
15 years 9 months ago
A Hardware Filesystem Implementation for High-Speed Secondary Storage
Platform FPGAs are capable of hosting entire Linuxbased systems including standard peripherals, integrated network interface cards and even disk controllers on a single chip. File...
Ashwin A. Mendon, Ron Sass
GLOBECOM
2007
IEEE
15 years 9 months ago
Aggregated Bloom Filters for Intrusion Detection and Prevention Hardware
—Bloom Filters (BFs) are fundamental building blocks in various network security applications, where packets from high-speed links are processed using state-of-the-art hardwareba...
N. Sertac Artan, Kaustubh Sinkar, Jalpa Patel, H. ...
MICRO
2007
IEEE
168views Hardware» more  MICRO 2007»
15 years 9 months ago
Global Multi-Threaded Instruction Scheduling
Recently, the microprocessor industry has moved toward chip multiprocessor (CMP) designs as a means of utilizing the increasing transistor counts in the face of physical and micro...
Guilherme Ottoni, David I. August
112
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IWMM
2007
Springer
116views Hardware» more  IWMM 2007»
15 years 9 months ago
Heap space analysis for java bytecode
This article presents a heap space analysis for (sequential) Java bytecode. The analysis generates heap space cost relations which define at compile-time the heap consumption of ...
Elvira Albert, Samir Genaim, Miguel Gómez-Z...
CODES
2006
IEEE
15 years 9 months ago
A multiprocessing approach to accelerate retargetable and portable dynamic-compiled instruction-set simulation
Traditionally, instruction-set simulators (ISS’s) are sequential programs running on individual processors. Besides the advances of simulation techniques, ISS’s have been main...
Wei Qin, Joseph D'Errico, Xinping Zhu