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DAC
2002
ACM
16 years 2 months ago
Petri net modeling of gate and interconnect delays for power estimation
In this paper, a new type of Petri net called Hierarchical Colored Hardware Petri net, to model real-delay switching activity for power estimation is proposed. The logic circuit i...
Ashok K. Murugavel, N. Ranganathan
ICCD
2005
IEEE
116views Hardware» more  ICCD 2005»
15 years 11 months ago
Enhanced Dual-Transition Probabilistic Power Estimation with Selective Supergate Analysis
Consideration of pairs of transition in probabilistic simulation allows power estimation for digital circuits in which inertial delays can filter glitches [5]. However, the merit ...
Fei Hu, Vishwani D. Agrawal
ISCAS
2006
IEEE
93views Hardware» more  ISCAS 2006»
15 years 8 months ago
Radial distribution power flow studies in a remotely distributed environment
—With the continued push toward dispersed generation and distributed intelligent devices throughout the distribution system, a proper analysis method for understanding the operat...
Michael Kleinberg, Karen Miu, Chika O. Nwankpa
ISVLSI
2006
IEEE
150views VLSI» more  ISVLSI 2006»
15 years 8 months ago
Design and Analysis of a Low Power VLIW DSP Core
Power consumption has been the primary issue in processor design, with various power reduction strategies being adopted from system-level to circuitlevel. In order to develop a po...
Chan-Hao Chang, Diana Marculescu
ISCAS
2005
IEEE
135views Hardware» more  ISCAS 2005»
15 years 7 months ago
Dual use of power lines for data communications in a system-on-chip environment
—We propose to use power pins to simultaneously carry data signals while delivering its power. A direct superposition of a data signal on a power pin would fail due to an inheren...
Woo Cheol Chung, Dong Sam Ha, Hyung-Jin Lee